Siffer

Many years ago, I thought that circuit diagrams was the only way to reason about electronics and logic.

In fact I only lived in the analog world at the time, with transistors and resistors.

Then I started studying at LiTH and learned more about analog electronics, and really got introduced to digital electronics. That shit was rad! Just connect pins of standard circuits to create advanced shit like counters and serial buffers and things that is straight up overwhelming to design as analog circuits!

Then the courses slowly transitioned into how to compose more even advanced functionality, and finally into composing those functions into simple CPU architectures!

At this point we still drew schematics for things and used this as the perspective to reason around. Then we got introduced to VHDL and things started taking off for real! Within a few weeks we had to design and implement functioning CPU architectures on CPLDs.

It wasn't a game-changer at the time. But now it seems like the simplest thing to project the idea of what you want into VHDL. Schematics and diagrams are still of help of course, but any single subcircuit is easy to express.

For the uninitiated

VHDL is one of two major HDL (Hardware Description Language) available, the other being Verilog. Verilog is similar in syntax to C, while VHDL is similar in syntax to Ada. I personally prefer the explicit and verbose syntax of VHDL. Verilog to me looks like someone made an ugly hack and everybody just rolled with it.

Anyway, what the languages boil down to is to be able to say that

That's what it is in simple terms.

Click here to view the corresponding VHDL 
-- this is the entity
entity Magic is
  port ( 
    i1 : in std_logic;
    i2 : in std_logic;
    o1  : out std_logic);
end entity Magic;

-- this is the architecture
architecture RTL of Magic is
  component AND
    port ( Ai1 : in std_logic; 
           Ai2 : in std_logic; 
           Ao1 : out std_logic ); 
  end component;

  component NOT
    port ( Bi1 : in std_logic; 
           Bo1 : out std_logic ); 
  end component;
begin
  -- Here we say that we have a signal called `wire1`.
  signal wire1 : std_logic;

  -- Create an AND-gate called A, and connect input from Magic to it.
  -- Output is into the signal `wire`
  A : AND port map (
    Ai1 <= i1,
    Ai2 <= i2,
    Ao1 <= wire1
  ); 
  -- Create NOT-circuit called B.
  -- Input is the signal `wire` which is connected to the output of A
  -- Output is connected to the output of Magic
  B : NOT port map (
    Bi1 <= wire,
    Bo1 <= o1
  ); 
end architecture RTL;


Now, as basic logic like AND, OR, NOT, etc is very common building blocks, we there is language support for being able to express that without expicitly declaring all internal" chips and connections they require. A functional equivalent would be

This is a lot easier and a lot more concise to express than the earlier version, and thus easier to work with.

Click here to view the corresponding VHDL 
-- this is the entity
entity Magic is
  port ( 
    i1 : in std_logic;
    i2 : in std_logic;
    o1  : out std_logic);
end entity Magic;

architecture RTL of Magic is
begin
  -- This is a lot more compact and concise. You could even do `o1 <= i1 nand i2;` directly!
  o1 <= not (i1 and i2);
end architecture RTL;


These are both two versions of what is called a netlist.

A netlist is a.. list, that describes the interconnectivity network of circuits.

The process of synthesizing VHDL(or any HDL) is the process of refining the netlists into less concise versions of themselves. After the netlist has been detailed all the way to only consist of individual AND, OR, NOT cells, it is said to be a logic-level netlist. Of course, depending on the target of the synthetization there might be higher-level gates available for common functions, like adders or memories.

We perform further synthetization from logic-level to gate-level, and during this we might map some logic to the existing adder-circuits available.

Regardless of the level where it is done, the term is technology mapping when mapping a netlist to existing building blocks. Technically mapping basic logic like AND is also technology mapping.

Logic networks can be transformed into multiple equivalent circuits. Sometimes an AIG is a good representation, where optimizations can be performed. But it could as well be that the logic is turned into a LUT, which can be realized with MUXes or ROM.

For FPGAs, technology mapping is often to rewrite logic circuits into fixed-sized LUTs.

For CPLDs, it could be to turn logic into ORs of ANDs (sum of products).

After a gate-level netlist has been produced, it is placed and routed. This corresponds to giving physical locations to the cells(placing) and making sure the right inputs/outputs can be connected (routing). This is kind of like solving a sudoku-puzzle; position the numbers(place) and make sure the constraints are fullfilled (routing is possible). Like in sudoku, something that is badly placed prevents you from solving the entire puzzle. If that happens, you try again until you make it.

Now there are a few common ways to synthezise to hardware

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